The present invention relates to a semiconductor device having a MOSFET for high voltage, such as a DMOSFET (Double Diffused MOSFET), mounted thereon or to an LSI having a bipolar transistor or CMOSFET in addition to the DMOSFET or the like and to a method of manufacturing the same.
In recent years, there have been an increasing number of proposals for integrating a semiconductor device of DMOS transistor (Double Diffused MOS Transistor) structure with a device of different type.
By way of example, a description will be given to a device obtained by integrating a semiconductor device of DMOS structure with a CMOS device with reference to FIGS. 20(a) and 20(b) and FIGS. 21(a) and 21(b). First, as shown in FIG. 20(a), an N.sup.- drain diffused layer 1002, a P.sup.- -well diffused layer 1003, and an N.sup.- -well diffused layer 1004 are sequentially formed on a P-type semiconductor substrate 1000 having a (100) plane as the main surface, followed by the formation of an isolation 1005 in the surface of the semiconductor substrate 1000 by selective oxidation process for defining a region in which a DMOSFET is to be formed, a region in which an NMOSFET is to be formed, and a region in which a PMOSFET is to be formed.
Next, as shown in FIG. 20(b), gate oxide films 1007 are formed and a polysilicon film 1008 is deposited thereon by low-pressure CVD. After an N.sup.+ gate electrode 1008a of the DMOSFET, an N.sup.+ gate electrode 1008b of the NMOSFET, and an N.sup.+ gate electrode 1008c of the PMOSFET are formed by using a resist film for forming gate electrodes (not shown), the resist film is removed. Subsequently, a new resist film 1009 is formed so that boron ions are selectively implanted into a region in which a source is to be formed (a region defined by the dashed curve and the line representing the surface of the P-type semiconductor substrate 1000) in an N.sup.- drain diffused layer 1002 of the DMOSFET by using the resist film 1009 and the N.sup.+ gate electrode 1008a of the DMOSFET as a mask, followed by a high-temperature drive-in process, thereby forming a P.sup.- body diffused layer 1014 shown in FIG. 21(a).
Then, as shown in FIG. 21(a), B.sup.+ ions are selectively implanted into only the region in which the PMOSFET is to be formed by using the resist film 1012 as a mask to control the threshold of the PMOSFET, thereby forming a P.sup.- diffused layer 1013 for Vt control.
Thereafter, as shown in FIG. 21(b), an N.sup.+ source diffused layer 1015 and an N.sup.+ drain diffused layer 1016 of the DMOSFET, an N.sup.+ source diffused layer 1017 and an N.sup.+ drain diffused layer 1018 of the NMOSFET, and a P.sup.+ source diffused layer 1019 and a P.sup.+ drain diffused layer 1020 of the PMOSFET are formed, followed by the formation of metal interconnections for the respective elements, thereby finishing the device.
In this manner, a composite LSI of a DMOS transistor and a CMOS transistor is manufactured.
However, a semiconductor device and a method of manufacturing the same as shown in FIGS. 20(a) and 20(b) and FIGS. 21(a) and 21(b) have the following problems.
(1) In the PMOSFET, the depth of the P.sup.- diffused layer 1013 for Vt control varies considerably since it is formed by forming the N.sup.+ gate electrode 1008c and then implanting B ions for Vt control through the gate electrode 1008c. If the depth of the P.sup.- diffused layer 1013 for Vt control varies in a PMOSFET having such a buried channel structure, the threshold Vt thereof varies greatly. Accordingly, variations in the threshold Vt of the PMOSFET are highly dependent on the film quality and thickness of the gate electrode 1008c which may influence the projected range (Rp) of the implanted B ions. When polysilicon is used as a material composing the gate electrode, in particular, a film of uniform quality cannot be formed because of grain size extremely difficult to control, which causes significant variations in the projected range (Rp) of the implanted B ions and in the threshold Vt of the PMOSFET. PA1 (2) As the gate oxide films 1007 become thinner with the increasing miniaturization of the device, the impurity in the gate electrodes is diffused into the channel regions through the gate oxide films 1007 by the high-temperature drive-in process performed after the formation of the respective gate electrodes 1008a, 1008b, and 1008c in the DMOSFET, NMOSFET, and PMOSFET to form the P.sup.- body diffused layer 1014 of the DMOSFET, which not only causes variations in threshold Vt but also reduces the reliability of the gate oxide films, since the impurity is diffused through the gate oxide films 1007.
To avoid the problems, the individual gate insulating films and gate electrodes of the DMOSFET and CMOSFET have been formed discretely in the conventional manufacturing process, which requires two steps of depositing a polysilicon film and two steps of patterning the polysilicon film, resulting in increased manufacturing cost and reduced production yield.
On the other hand, Japanese Laid-Open Patent Publication HEI 3-205832 discloses another method of manufacturing a semiconductor device having a DMOSFET on a semiconductor substrate.
First, as shown in FIG. 22(a), an insulated gate 1102 made of polysilicon or like material is formed on a surface of an N-type semiconductor substrate 1101 in which a drain is to be formed. Then, as shown in FIG. 22(b), a P-type body diffused layer 1103 is formed by using the insulated gate 1102 as a part of a mask. Subsequently, as shown in FIG. 22(c), a source diffused layer 1104 and a drain contact diffused layer 1105 are formed by using the insulated gate 1102 as a part of a mask. At this stage, a portion underlying the insulated gate 1102 and corresponding to a difference in lateral diffusion length between the body diffused layer 1103 and the source diffused layer 1104 forms a channel region 1106, thereby completing the formation of all the diffused layers. Thereafter, electrodes are formed at respective terminals to complete the device.
As shown in FIG. 22(d), there may be the case where the drain is withdrawn from a lower portion of the semiconductor substrate 1101. In that case, the drain contact diffused layer 1105 is formed over the entire back surface of the semiconductor substrate 1101.
However, in the above conventional method of manufacturing a semiconductor device having a DMOSFET, it has been difficult to reduce the on-resistance of the DMOSFET and suppress the activation of a parasitic bipolar transistor at the same time.
The on-resistance, which is the resistance between the source and drain of the DMOSFET when the DMOSFET is conducting, is desired to be low. To lower the on-resistance, however, the impurity concentration of the body diffused layer should be reduced, which may activate a parasitic NPN transistor using the source, body, drain of the DMOSFET as its emitter, base, and collector. This is because a substrate current Isub of the DMOSFET serves as a base current of the parasitic bipolar transistor, so that even an extremely small substrate current may activate the parasitic bipolar transistor if the impurity concentration of the body diffused layer is low.
On the other hand, if the impurity concentration of the body diffused layer is increased to suppress the activation of the parasitic transistor, the impurity concentration of the channel region near the surface of the body diffused layer is also increased, which increases the on-resistance. Moreover, the threshold voltage Vth of the DMOSFET is disadvantageously increased due to the increased impurity concentration of the body diffused layer.